1. Field of the Invention
This invention relates to a burn-in apparatus and method which is used in burn-in tests (high temperature operating tests) in which temperature loads and electric loads are applied during the testing of semiconductor devices.
2. Related Background Art
Burn-in tests are essential to the life estimating of semiconductor devices, and to the detection of infant mortality or early lifetime failures in screening processes. Generally, a burn-in test is conducted using burn-in boards 10 of FIG. 1 and a burn-in test chamber 12 of FIG. 2. Each burn-in board 10 includes a board 14 of a heat resistant resin or the like. This board 14 has a plurality of sockets 16 provided thereon for receiving DUTs (devices under test) or semiconductor devices (not shown), and external terminals 18 provided on one end of the board 14 for the electrical contact to the outside. The board 14 has a handle 20 provided on the opposite end for the manipulation of the burn-in board 10 by an operator. The terminals (not shown) of the sockets 16 are connected to the external terminals 18 by wirings 22 (partially shown in FIG. 1) on the board 14.
Such burn-in boards 10 are set in the burn-in test chamber 12 as shown in FIG. 2, More specifically, the burn-in test chamber 12 comprises a box body 24 as a main body, a lid 26 attached to the box 24 by a hinge mechanism 28, and a board connector 30 provided in the box body 24. The board connector 30 has slits 32 for receiving the boards 14 of the burn-in board 10. When the boards 14 are inserted into the slits 32 of the board connector 30, the external terminals 18 of the burn-in boards 10 and the terminals (not shown) of the board connector 30 are connected. Through this connection, an electric power is supplied to the semiconductor devices by a power supply means (not shown). Although not shown, the burn-in test chamber 12 includes a temperature adjusting means. The temperature adjusting means is generally in the form of a means for supplying heated air into the interior of the burn-in test chamber 12, or in the form of a heating means.
An interior temperature of the burn-in test chamber 12, i.e., an environmental temperature T.sub.a of the atmosphere surrounding the semiconductor devices is measured by a temperature sensor (not shown) disposed near the inner surface of the wall of the box 24. Conventional burn-in tests have been conducted by controlling the temperature adjusting means while monitoring measured temperatures (MIL-STD 883). But for the following reasons, such conventional art is insufficient to properly conduct the burn-in tests.
In the conventional art, what can be monitored real time is an environmental temperature T.sub.a of semiconductor devices, and this environmental temperature T.sub.a does not agree with a surface temperature of the semiconductor chips constituting the semiconductor devices, especially with junction temperatures T.sub.j at the pn junctions or Schottky junctions of the semiconductor chips. Since failures of semiconductor devices depend on these junction temperatures T.sub.j, for the efficient estimation of lives of semiconductor devices and the efficient detection of early lifetime failures of semiconductor devices without applying overloads to proper devices, it is preferable to conduct burn-in tests within a set junction temperature T.sub.j range. In the conventional burn-in tests, a junction temperature T.sub.j is estimated based on a measured environmental temperature T.sub.a, and burn-in tests is conducted based on the estimated junction temperature. But it needs very complicated operations to check relationships between an environmental temperature T.sub.a and a junction temperature T.sub.j, and different estimating operations are needed in accordance with different sizes types and specifications of semiconductor devices to be tested. Accordingly, it has been difficult to conduct simple burn-in tests with high precision. Additionally, the environmental temperature T.sub.a varies depending on locations in the burn-in test chamber 12, and heat generation amounts of respective semiconductor devices to be tested are not the same either. Therefore, it has not been easy to screen a number of semiconductor devices under uniform conditions.